Title :
Foreword to Special Issue on Aerospace Computers
Author :
Pasqaualini, Ronald
Author_Institution :
Philco-Ford Corp., Microelectronics Div.
Abstract :
This paper discusses the design trade-offs for a parallel bit-organized MOS memory. A memory capacity of 40K bits can be achieved using LSI techniques. Memory storage capacity is expandable in both word length and number of words stored. The physical dimensions of the memory should be considerably smaller than those of a comparable core design. Power consumption per bit should likewise be less than that achievable with cores. A full cycle time of 1 us or less can be achieved. Cost per bit should compare very favorably with that of a core design.
Keywords :
Aerospace electronics; Aerospace engineering; Computer displays; Ground support; Magnetic recording; Military computing; Space technology; System analysis and design; Systems engineering and theory; Transistors; Address selection technique; address registers; chip interconnection considerations; fan-in considerations; fan-out considerations; implementation of input; memory interface with the computer; multilayer processing increases speed and decreases cell size; number of transistors and leads on the memor chip; organization of the memory chip; output; output logic for memory chip; solutions to the fan-out problem; total number of chips in the memory;
Journal_Title :
Electronic Computers, IEEE Transactions on
DOI :
10.1109/PGEC.1967.264739
