Title :
Fast-locking CDR circuit with autonomously reconfigurable mechanism
Author :
Woo, J.-K. ; Jeong, D.K. ; Kim, S.
Author_Institution :
Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul
Abstract :
A new fast-locking scheme is applied to a clock and data recovery (CDR) circuit based on a phase-locked loop. Locking time is reduced by using an autonomously reconfigurable charge pump and loop filter. A 1.25 Gbit/s prototype CDR circuit has been implemented in a 0.18 mum CMOS technology.
Keywords :
CMOS integrated circuits; clocks; phase locked loops; synchronisation; CDR circuit; CMOS technology; autonomously reconfigurable mechanism; bit rate 1.25 Gbit/s; clock and data recovery circuit; fast-locking scheme; loop filter; phase locked loop; reconfigurable charge pump; size 0.18 mum;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20070036
