An Optimally Designed Process for Submicrometer MOSFET´s

Author

Shibata, Tadashi ; Hieda, Katsuhiko ; Sato, Masaki ; Konaka, Masami ; Luong, Ryo ; Dang, Mo ; Iizuka, Hisakazu

Volume

17

Issue

2

fYear

1982

fDate

4/1/1982 12:00:00 AM

Firstpage

161

Lastpage

165

Abstract

An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET´s. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 /spl mu/m. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.

Keywords

Field effect integrated circuits; Insulated gate field effect transistors; Integrated circuit technology; Large scale integration; Circuit optimization; Degradation; Doping; Fabrication; Implants; Integrated circuit interconnections; MOSFET circuits; Process design; Silicidation; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1982.1051710

Filename

1051710