• DocumentCode
    892373
  • Title

    Concurrent Error Detection and Testing for Large PLA´s

  • Author

    Khakbaz, Javad ; McCluskey, Edward J.

  • Volume
    17
  • Issue
    2
  • fYear
    1982
  • fDate
    4/1/1982 12:00:00 AM
  • Firstpage
    386
  • Lastpage
    394
  • Abstract
    A system of checkers is designed for concurrent error detection in large PLA´s. This system combines concurrent error detection with off-lime functional testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection.
  • Keywords
    Cellular arrays; Error detection; Integrated circuit testing; Integrated logic circuits; Large scale integration; Logic testing; Circuit testing; Costs; Digital systems; Fault detection; Hardware; Logic arrays; Logic testing; Programmable logic arrays; System testing; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1982.1051746
  • Filename
    1051746