Title :
Nanosecond NMOS VLSI Current Mode Logic
Author :
Elmasry, Mohamed I.
fDate :
4/1/1982 12:00:00 AM
Abstract :
Current mode logic (CML) is used to obtain NMOS VLSI logic gates with nanosecond delays at a speed power product of 1.5 pJ. The gates use a reference voltage generated by the difference between an enhancement- and a depletion-type MOSFET. A depletion-type MOSFET is used for the current sources and the loads. The gates have been designed with a logic swing of 2 V in a 2.5-μm NMOS VLSI technology, simulated, and their circuit performance is studied.
Keywords :
Emitter-coupled logic; Field effect integrated circuits; Integrated logic circuits; Large scale integration; Circuit optimization; Circuit simulation; Delay; Logic circuits; Logic design; Logic gates; MOS devices; MOSFET circuits; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1982.1051750
