Title :
A 35 ns 16K NMOS static RAM
Author :
Anami, Kenji ; Yoshimoto, Masahiko ; Shinohara, Hirofumi ; Hirata, Yoshihiro ; Harada, Hiroshi ; Nakano, Takao
Abstract :
An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.
Keywords :
Field effect integrated circuits; field effect integrated circuits; CMOS technology; Circuits; Conductivity; Decoding; Delay effects; Large scale integration; MOS devices; Optical amplifiers; Power dissipation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1982.1051824
