Title :
An 80 ns 32K EEPROM using the FETMOS cell
Author :
Kuo, Clinton ; Yeargain, John R. ; Downey, William J., III ; Ilgenstein, Kerry A. ; Jorvig, Jeffrey R. ; Smith, Stiephen L. ; Bormann, Alan R.
Abstract :
A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O´ program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.
Keywords :
Field effect integrated circuits; field effect integrated circuits; Costs; Dielectric devices; Dielectric substrates; EPROM; Electron emission; Electron traps; Nonvolatile memory; Testing; Tunneling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1982.1051825
