DocumentCode :
893188
Title :
A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features
Author :
Yaron, Giora ; Prasad, S. Jayasimha ; Ebel, Mark S. ; Leong, Bruce M K
Volume :
17
Issue :
5
fYear :
1982
Firstpage :
833
Lastpage :
840
Abstract :
Reports on a new 200 ns highly reliable, 16384 bit (2K/spl times/8), thin oxide floating gate electrically erasable and programmable read-only memory-e/SUP 2/PROM. The part can be written and erased by tunneling of electrons to and from the floating gate within 10 ms by applying a DC signal of 21 V to V/SUB pp/ . Improved yield and performance through minimizing the thin oxide area is achieved by incorporating a single direct wafer stepper masking step to define a minimum (1.5 /spl mu/m diameter) thin oxide injecting area. A new array architecture has made it feasible to selectively erase or write a single byte. Improved reliability is achieved by incorporating an on-chip V/SUB pp/ pulse shape generator which minimizes thin oxide stress. Endurance related testing features designed into the part allow efficient endurance screening of potentially `weak´ parts.
Keywords :
Circuit reliability; circuit reliability; Charge carrier processes; Electron traps; Isolation technology; Nonvolatile memory; PROM; Pulse generation; Pulse shaping methods; Shape; Stress; Tunneling;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1982.1051827
Filename :
1051827
Link To Document :
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