Abstract :
Describes a new approach to circuit design that allows charge-coupled devices to perform combinatorial digital logic. These circuits use charge packets, floating gates, and conventional NMOS circuitry in a way that combines the low power, high packing density of CCDs with some of the high-speed combinatorial logic capabilities of conventional NMOS circuits. Since only a few transfers are involved in the operation of these circuits, charge transfer efficiency is not a critical parameter. A CCD ripple adder is described that has been designed, fabricated, and tested, and a charge control analysis has been used to estimate its ultimate speed capabilities. An arithmetic logic unit design is also described. The combinatorial CCD circuits are particularly well suited to previous digital CCD logic approaches in that they allow elimination of power and space-consuming storage registers. These circuits are most useful in applications requiring large, regular, pipelined architectures such as systolic arrays where the critical performance parameter is throughput per unit power.
