• DocumentCode
    893642
  • Title

    Parasitic bulk resistances in junction-gate FETs

  • Author

    Grebene, A.B.

  • Volume
    55
  • Issue
    11
  • fYear
    1967
  • Firstpage
    2031
  • Lastpage
    2032
  • Abstract
    A practical method for evaluating parasitic bulk resistances in junction FETs is described. The method does not require a knowledge of the actual device geometry or dimensions. It is shown that parasitic bulk resistances make up a substantial portion of measured open-channel resistance.
  • Keywords
    Artificial intelligence; Contact resistance; Control systems; Electrical resistance measurement; FETs; Frequency; Geometry; Iterative algorithms; Resistors; Sampling methods;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1967.6049
  • Filename
    1447979
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=893642