A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

Author

Sun, Kuo-Jung ; Tsai, Zuo-Min ; Lin, Kun-You ; Wang, Huei

Author_Institution

Graduate Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

54

Issue

4

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1554

Lastpage

1560

Abstract

A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.

Keywords

CMOS integrated circuits; MMIC amplifiers; circuit optimisation; inductors; integrated circuit noise; low noise amplifiers; mixed analogue-digital integrated circuits; 0.18 micron; 10 GHz; 11.25 dB; 2.9 dB; CMOS LNA; CMOS low-noise amplifiers; CMOS technology; noise figure; noise optimization formulation; on-chip low-Q inductors; power gain; series resistances; CMOS technology; Electrical resistance measurement; Frequency measurement; Gain measurement; Inductors; Low-noise amplifiers; Noise figure; Noise measurement; Power measurement; Radio frequency; CMOS; low-noise amplifier (LNA);

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2006.871365

Filename

1618575