Fan out and speed of GaAs SDFL logic

Analyses the fan-out capability and speed of a Schottky diode-FET logic (SDFL) gate in the context of an analytical model which links the fan-out to the parameters of the pull-up, pull-down, and switching transistors, and to the supply voltages. The analysis shows that for higher fan-outs increasing the pull-up to pull-down current ratio should increase the speed; and that to some extent the maximum fan-out can be increased by raising the positive supply voltage. It also demonstrates the decrease in the logic swing with the increase of the fan-out. Computer simulation of inverter chains and ring oscillators with different fan-outs is in good agreement both with the analytical model and experimental results. The results lead to an approximate relation between the time delay per gate and fan-out for an SDLF gate.