DocumentCode
893801
Title
Effective heuristic algorithms for VLSI-circuit partition
Author
Tao, L. ; Zhao, Y.C.
Author_Institution
Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
Volume
140
Issue
2
fYear
1993
fDate
4/1/1993 12:00:00 AM
Firstpage
127
Lastpage
134
Abstract
The paper studies the multiway graph-partition problem for VLSI circuit partition. Given a graph representing a VLSI circuit, the graph vertices are partitioned into mutually exclusive subsets to minimise the total weights for edges crossing the subsets under the constraint that the vertex weights are evenly distributed among the subsets. Simulated annealing and tabu search are adapted to solve this problem based on a special neighbourhood design. A new general optimisation paradigm, called stochastic probe, is then proposed to integrate the advantages of the above two approaches. Extensive experimental study shows that all three new algorithms produce significantly better solutions than the LPK algorithm reported by Lee, Park and Kim, and that the stochastic probe algorithm always produces the best solution among all the four algorithms with a running time comparable with that for the LPK algorithm
Keywords
VLSI; circuit layout; graph theory; network routing; network topology; VLSI-circuit partition; edges; graph vertices; heuristic algorithms; multiway graph-partition problem; mutually exclusive subsets; neighbourhood design; running time; stochastic probe; tabu search; total weights;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
212641
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