10 ns 8x8 multiplier LSI using super self-aligned process technology

Describes a high-speed 8/spl times/8 bit multiplier LSI which uses the newly developed high-speed and low-power bipolar process technology SST-2. SST-2 results in 250 ps delay time and 0.165 pJ power delay product in a low-level current mode logic (LCML) gate. Its multiplication time is about 10 ns, and its power dissipation is about 660 mW. This LSI has a feature called `perfect expandability´ for arbitrary scaling of the expanded 8n/spl times/8n bit multiplier without an additional circuit. The results indicate that 32/spl times/32 bit multiplication can be carried out with 55 ns.