Title :
A 90 ns 256K x 1 bit DRAM with double-level Al technology
Author :
Fujii, Takeo ; Mitake, Kenjiro ; Tada, Kazuhiro ; Inoue, Yasukazu ; Watanabe, Hiroshi ; Kudoh, Osamu ; Yamamoto, Hirohiko
Abstract :
A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Decoding; Driver circuits; Dry etching; Electric variables; Error analysis; Integrated circuit interconnections; National electric code; Random access memory; Read-write memory; Sputtering;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1051974