DocumentCode
894571
Title
A 70 ns high density 64K CMOS dynamic RAM
Author
Chwang, Ronald J C ; Choi, Mike ; Creek, Dan ; Stern, Seth ; Pelley, Perry H. ; Schutz, Joseph D. ; Warkentin, Paul A. ; Bohr, Mark T. ; Yu, Ken
Volume
18
Issue
5
fYear
1983
Firstpage
457
Lastpage
463
Abstract
A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; Redundancy; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; redundancy; Boron; CMOS memory circuits; CMOS technology; DRAM chips; Error analysis; Implants; MOS devices; Protection; Random access memory; Redundancy;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1983.1051978
Filename
1051978
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