• DocumentCode
    894610
  • Title

    A 25 ns 8K x 8 static MTL/I/sup 2/L RAM

  • Author

    Wiedmann, Siegfried K. ; Heuber, Klaus H.

  • Volume
    18
  • Issue
    5
  • fYear
    1983
  • Firstpage
    486
  • Lastpage
    494
  • Abstract
    An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.
  • Keywords
    Bipolar integrated circuits; Integrated circuit technology; Integrated injection logic; Integrated memory circuits; Large scale integration; Random-access storage; bipolar integrated circuits; integrated circuit technology; integrated injection logic; integrated memory circuits; large scale integration; random-access storage; Circuit stability; Equivalent circuits; Flip-flops; Power distribution; Read-write memory; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1983.1051982
  • Filename
    1051982