Title :
A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions
Author :
Knecht, Mark W. ; Manley, Martin H. ; Perasso, David C. ; Thomas, Jack F. ; Keshtbod, Parviz ; Tandan, Naresh ; Simmons, George H.
Abstract :
A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated circuit testing; Integrated memory circuits; Large scale integration; PROM; field effect integrated circuits; integrated circuit technology; integrated circuit testing; integrated memory circuits; large scale integration; CMOS process; CMOS technology; Circuit testing; Clocks; EPROM; MOS devices; Microprocessors; Power dissipation; Power generation; Signal generators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1051993
