DocumentCode :
894732
Title :
A multiplexed 4 Mbit bubble memory device
Author :
Washburn, H. ; Silverman, P.
Volume :
18
Issue :
5
fYear :
1983
Firstpage :
567
Lastpage :
571
Abstract :
A 4-Mbit magnetic bubble memory has been designed and demonstrated which is architecturally compatible with an 1-Mbit memory. The design goals for the memory were to achieve user software compatibility and pin-for-pin interchangeability. To achieve this, one key 4-Mbit device feature was additional multiplexing. This was obtained by a novel application of thin-film detectors and replicate generators along with other function designs. The result is a 4 bit/cycle write and read operation and a page length of 512 bits. The margins for the functions are shown to be comparable to those for the 1-Mbit process while the detector signal is over three times larger. The 1-Mbit process is extended to the 4-Mbit device by adding a thin permalloy level which requires one additional critical alignment and scaling geometries to give a 0.75-/spl mu/m minimum feature size on a 5.5-/spl mu/m square memory cell.
Keywords :
Magnetic bubble memories; magnetic bubble memories; DRAM chips; Detectors; EPROM; Fault tolerance; Random access memory; Read-write memory; Redundancy; Silicon; Solid state circuits; Very large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1983.1051995
Filename :
1051995
Link To Document :
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