Title :
Design and fabrication of depletion GaAs LSI high-speed 32-bit adder
Author :
Yamamoto, Ryuichiro ; Higashisaka, Asamitsu ; Asai, Shuji ; Tsuji, Tsutomu ; Takayama, Yoichiro ; Yano, Seiken
Abstract :
A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.
Keywords :
Adders; Field effect integrated circuits; Gallium arsenide; III-V semiconductors; Integrated circuit technology; Integrated logic circuits; Large scale integration; adders; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated logic circuits; large scale integration; Diodes; FETs; Fabrication; Gallium arsenide; High speed integrated circuits; Large scale integration; Logic design; Logic gates; Power dissipation; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1051999
