A GaAs 16x16 bit parallel multiplier

Author

Nakayama, Yoshiro ; Suyama, Katsuhiko ; Shimizu, Haruo ; Yokoyama, Naoki ; Ohnishi, Hiroaki ; Shibatomi, Akihiro ; Ishikawa, Hajime

Volume

18

Issue

5

fYear

1983

Firstpage

599

Lastpage

603

Abstract

A GaAs 16/spl times/16-bit parallel multiplier has been constructed using a direct-coupled FET logic (DCFL) circuit with tungsten silicide gate self-aligned technology. This circuit chip, containing 3168 NOR gates with 2-/spl mu/m gate length enhancement/depletion FETs, is the most complex GaAs integrated circuit reported to date. MESFETs with the gate finger oriented in the [011] direction, which showed a smaller threshold voltage deviation, were used to realize this 3000-gate LSI. This multiplier has a multiply time of 10.5 ns, with a power dissipation of 952 mW at a supply voltage of 1.6 V. The projected performance, assuming 1-/spl mu/m gate length, is a multiply time of 6.5 ns.

Keywords

Digital integrated circuits; Field effect integrated circuits; Gallium arsenide; III-V semiconductors; Integrated circuit technology; Large scale integration; Multiplying circuits; digital integrated circuits; field effect integrated circuits; gallium arsenide; integrated circuit technology; large scale integration; multiplying circuits; FETs; Fingers; Gallium arsenide; Integrated circuit technology; Large scale integration; Logic circuits; MESFETs; Silicides; Threshold voltage; Tungsten;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1983.1052000

Filename

1052000