Title :
A novel NMOS E/sup 2/PROM scheme
Abstract :
A new NMOS E/SUP 2/PROM scheme is proposed by which the conventional erase-then-write two-step byte write operation can be realized in one step. Only those bits that do not match the data to be written will be inverted.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Large scale integration; PROM; field effect integrated circuits; integrated memory circuits; large scale integration; Capacitors; Charge pumps; Clocks; Impedance; Latches; Logic circuits; MOS devices; PROM; Tunneling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1052002
