Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization

In many embedded systems, particularly those with high data computations, the delay of memory access is one of the major bottlenecks in the system´s performance. It has been known that there are high variations in memory-access delays depending on the ways of designing memory configurations and assigning arrays to memories. Furthermore, embedded-DRAM technology that provides efficient access modes is actively being developed, possibly becoming a mainstream in future embedded-system design. In that context, in this paper, the authors propose an effective solution to the problem of (embedded DRAM) memory allocation and mapping in memory-access-code generation with the objective of minimizing the total memory-access time. Specifically, the proposed approach, called memory-access-code optimization (MACCESS-opt), solves the three problems simultaneously: 1) determination of memories; 2) mapping of arrays to memories; and 3) scheduling of memory-access operations, so that the use of DRAM-access modes is maximized while satisfying the storage size constraint of embedded systems. Experimental data on a set of benchmark designs are provided to show the effectiveness of the proposed integrated approach. In short, MACCESS-opt reduces the total memory-access latency by over 18%, from which the authors found that the memory mapping and scheduling techniques in MACCESS-opt contribute about 12% and 6% reductions of the total memory-access latency, respectively