ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis

Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analysis must be embedded within IC synthesis. However, this requires accurate three-dimensional chip-package heat flow analysis. This has typically been based on numerical methods that are too computationally intensive for numerous repeated applications during synthesis or design. Thermal analysis techniques must be both accurate and fast for use in IC synthesis. This paper presents a novel accurate incremental spatially and temporally adaptive chip-package thermal analysis technique called ISAC for use in IC synthesis and design. It is common for IC temperature variation to strongly depend on position and time. ISAC dynamically adapts spatial- and temporal-modeling granularities to achieve high efficiency while maintaining accuracy. Both steady-state and dynamic thermal analyses are accelerated by the proposed heterogeneous spatial-resolution adaptation and asynchronous thermal-element time-marching techniques. Each technique enables orders-of-magnitude improvement in performance while preserving accuracy when compared with other state-of-the-art adaptive steady-state and dynamic IC thermal analysis techniques. Experimental results indicate that these improvements are sufficient to make accurate dynamic and steady-state thermal analysis practical within the inner loops of IC synthesis algorithms. ISAC has been validated against reliable commercial thermal analysis tools using industrial and academic synthesis test cases and chip designs. It has been implemented as a software package suitable for integration in IC synthesis and design flows and has been publicly released