A CMOS switched-capacitor variable line equalizer

The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.