DocumentCode
895572
Title
A subnanosecond 2000 gate array with ECL 100K compatibility
Author
Sato, Fumihiko ; Takahashi, Toru ; Misawa, Hiroyuki ; Kimura, Kodo
Volume
19
Issue
1
fYear
1984
Firstpage
5
Lastpage
9
Abstract
Describes a subnanosecond-gate array with 2000 gates fabricated by an advanced bipolar process. A 700-ps delay time was achieved for a basic ECL gate under a general usage condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, with power dissipation of 1.9 mW/gate. A 450-MHz typical toggle frequency has been obtained by using a series-gated flip-flop. Utilizing an integrated computer-aided design system, 100% routability has been attained for automatic placement and wiring in spite of 90% cell utilization. Low thermal resistance (6/spl deg/C/W) packages are used for this LSI chip to permit its installation in an air-cooled system.
Keywords
Bipolar integrated circuits; bipolar integrated circuits; Capacitance; Delay; Design automation; Frequency; Logic arrays; Logic circuits; Logic design; Packaging; Thermal resistance; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052077
Filename
1052077
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