DocumentCode
895601
Title
Automated gate array scaling
Author
Reasoner, Kelly J. ; Akers, Lex A. ; Still, David W.
Volume
19
Issue
1
fYear
1984
Firstpage
23
Lastpage
25
Abstract
A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
Keywords
Cellular arrays; cellular arrays; Algorithm design and analysis; Integrated circuit manufacture; Integrated circuit technology; Interpolation; Logic; Resistors;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052079
Filename
1052079
Link To Document