A mixed EFL/I/sup 2/L digital telecommunication integrated circuit

A bipolar integrated circuit has been designed as part of a VLSI upgrade of an existing digital switching circuit. The chip exploits the OXIL (oxide isolated) process which makes it possible to use both high-gain `up´ and `down´ devices, for I/SUP 2/L (integrated injection logic) and EFL (emitter function logic) respectively. This allowed the circuit designers to tailor power consumption, circuit speed, and gate density as needed. In particular, the high-speed properties of EFL were utilized in the control section to provide accurate timing signals and satisfy tight propagation delay requirements in the register section. I/SUP 2/L, because of its greater density and low power, was used in the gate-intensive register sections. Another novel feature is the treatment of bus lines (up to 250 fanout) such as clock, clear, etc., in the I/SUP 2/L sections. The common multiline I/SUP 2/L drive problem has been overcome by using high-drive translators from EFL circuitry and a single pullup resistor per bus line to provide switched currents to all gates on that line.