• DocumentCode
    895633
  • Title

    A three-dimensional CMOS design methodology

  • Author

    Hoefflinger, Bernd ; Liu, Sie T. ; Vajdic, Branislav

  • Volume
    19
  • Issue
    1
  • fYear
    1984
  • Firstpage
    37
  • Lastpage
    39
  • Abstract
    A technology-updatable design methodology for three-dimensional CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: (1) technology level, (2) mask level, (3) transistor level, and (4) logic level. A novel transistor-level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples are presented.
  • Keywords
    Circuit CAD; circuit CAD; Acoustical engineering; CMOS technology; Design engineering; Design methodology; Electrical engineering; Inverters; Isolation technology; Logic circuits; Silicon on insulator technology; Thin film transistors;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1984.1052082
  • Filename
    1052082
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=895633