Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips

The binary-tree-dynamic RAM (TRAM) architecture has been proposed to overcome the performance and testing time limits of the traditional architecture of memory chips. A 64-Mb prototype of this architecture is being built. The author investigates manufacturing yield and operational performance of redundant TRAMs with respect to variation of tree depth and redundancy level. For this purpose, a based chip area, a yield and operational performance figure of merit allowing the comparison of various choices, has been formulated and used. The yield is evaluated by a new Markov-chain-based model. The memory operational performance has been analyzed by an innovative technique that substitutes the notion of chip state at the end of the mission time with the cumulative work performed by the chip during the mission time (performability). Optimum values of three tree depth and redundancy level were found for a given RAM size, the adopted reconfiguration strategy, and the kinds of redundancy