An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

Author

Kim, Kyu-hyoun ; Chung, Hoe-Ju ; Kim, Woo-Seop ; Park, Moonsook ; Jang, Young-Chan ; Kim, Jin-Young ; Park, Hwan-Wook ; Kang, Uksong ; Coteus, Paul W. ; Choi, Joo Sun ; Kim, Changhyun

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY

Volume

42

Issue

1

fYear

2007

Firstpage

193

Lastpage

200

Abstract

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns

Keywords

DRAM chips; SRAM chips; clocks; 10 bit; 288 MByte; 8 Gbit/s; 9.6 ns; I/O error detection scheme; SDRAM; deca-data rate clocking scheme; memory interface; multiphase clock generation; Bandwidth; Cache memory; Central Processing Unit; Circuits; Clocks; Costs; Frequency; Random access memory; SDRAM; Timing; CRC; deca-data rate; memory interface; multi-phase clock generation; synchronous DRAM;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.888297

Filename

4039590