DocumentCode
895763
Title
Efficient instruction sequencing with inline target insertion
Author
Hwu, Wen-Mei W. ; Chang, Pohua P.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Volume
41
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1537
Lastpage
1551
Abstract
Inline target insertion, a specific compiler and pipeline implementation method for delayed branches with squashing, is defined. The method is shown to offer two important features not discovered in previous studies. First, branches inserted into branch slots are correctly executed. Second, the execution returns correctly from interrupts or exceptions with only one program counter. These two features result in better performance and less software/hardware complexity than conventional delayed branching mechanisms
Keywords
parallel programming; pipeline processing; program compilers; branch slots; compiler; delayed branches; exceptions; inline target insertion; instruction sequencing; interrupts; pipeline; program counter; squashing; Aerospace engineering; Counting circuits; Delay; Hardware; Helium; Logic; NASA; Pipeline processing; Software performance; Software systems;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.214662
Filename
214662
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