Learning probabilistic RAM nets using VLSI structures

Author

Clarkson, Trevor G. ; Gorse, Denise ; Taylor, J.G. ; Ng, C.K.

Author_Institution

Dept. of Electron. & Electr. Eng., King´´s Coll., London, UK

Volume

41

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1552

Lastpage

1561

Abstract

Hardware-realizable learning probabilistic RAMs (pRAMs) which implement local reinforcement rules utilizing synaptic rather than threshold noise in the stochastic search procedure are described. The design allows for both global and local rewards and penalties (in this latter case implementing a modified version of backpropagation). The architecture allows for serial updating of the weights of a pRAM net according to a reward/penalty learning rule. It is possible to generate a new set of pRAM outputs at least every 100 μs, which is faster than the response time of biological neurons

Keywords

VLSI; backpropagation; content-addressable storage; neural nets; RAM nets; VLSI structures; backpropagation; global penalties; global rewards; learning probabilistic RAMs; learning rule; local penalties; local reinforcement rules; local rewards; serial updating; stochastic search; synaptic noise; weights; Biological system modeling; Control systems; Hardware; Motion control; Neural networks; Neurons; Phase change random access memory; Read-write memory; Stochastic processes; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.214663

Filename

214663