DocumentCode
895860
Title
High-speed addition in CMOS
Author
Quach, Nhon T. ; Flynn, Michael J.
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA, USA
Volume
41
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1612
Lastpage
1615
Abstract
A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware
Keywords
CMOS integrated circuits; adders; 32 bit; CMOS; Ling-type 32-bit adder; carry look-ahead; gate delay; high speed addition; serial transistors; static complementary metal-oxide semiconductor; worst-case critical path; Adders; CMOS logic circuits; CMOS technology; Delay effects; Equations; Hardware;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.214671
Filename
214671
Link To Document