Title :
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit
Author :
Wijeratne, Sapumal B. ; Siddaiah, Nanda ; Mathew, Sanu K. ; Anders, Mark A. ; Krishnamurthy, Ram K. ; Anderson, Jeremy ; Ernest, Matthew ; Nardin, Mark
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
This paper describes a fourth generation Intel Pentium 4 processor integer execution core operating at 9 GHz in a 1.3-V, 65-nm CMOS technology at 70degC. Low-voltage-swing circuits of the 90-nm design are replaced by: 1) 2times frequency fast clock (FCLK)-optimized domino clocking scheme; 2) segmented arithmetic and logic unit (ALU) front-end multiplexer; 3) sparse-tree ALU adder; 4) merged add/subtract sparse-tree address generation unit (AGU) design; 5) speculative RC-delay-optimized rotator; and 6) single-rail L0 cache and alignment multiplexer, resulting in 8.4% reduction in integer core normalized active power and 42% reduction in normalized leakage power. The use of standard domino/static tools and methodologies lowers design complexity, reducing development cost and time. The redesign also reduces integer core thermal density, resulting in an 8degC reduction in CPU operating temperature
Keywords :
CMOS integrated circuits; cache storage; clocks; digital arithmetic; integrated circuit design; low-power electronics; microprocessor chips; switching circuits; 1.3 V; 65 nm; 70 C; 9 GHz; 90 nm; CMOS technology; Intel Pentium 4 processor; address generation unit; arithmetic and logic unit; frequency fast clock; integer execution core; leakage power; low voltage swing circuits; sparse tree; Adders; Arithmetic; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Frequency; Logic circuits; Logic design; Multiplexing; ALU shifter/rotator; Address generation unit; arithmetic and logic unit; integer execution unit; sparse tree;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.885055
