A systolic redundant residue arithmetic error correction circuit

In highly integrated processors, a concurrent fault tolerance capability is particularly important, especially for real-time applications. In fact, in these systems, transient errors are often present, but are difficult to correct online. Error recovery procedures applied for each processing or memory element require large amount of hardware and can reduce throughput. Residue arithmetic has intrinsic fault tolerance capability and requires less complex hardware. A single error correction procedure based on the use of a redundant residue number system (RRNS) and the base extension operation is proposed. The method uses a very small decision table and works in parallel mode; therefore it is suitable for high speed VLSI circuit realization. A parallel systolic architecture which realizes the algorithm is introduced