Latchup in Bipolar LSI Devices

A latchup analysis procedure for four layer (pnpn) latchup is presented and applied to specific bipolar LSI devices representative of several current bipolar LSI technologies. Radiation tests were performed to verify the results of the analysis. The analysis procedure consists of a) identifying all parasitic pnpn paths on the microcircuit, b) characterizing the paths to determine if they can be latched under worst case bias conditions and c) analyzing the pnpn path within the context of the circuit to determine if latchup can be sustained under normal operating conditions. The characterization phase is further supported by analytical studies to determine what design and processing variables may be altered to insure that latchup will not occur. The results of the analysis are that a.) nonisolated I2L is immune from latchup, b.) oxide-separated technologies can easily be made immune to latchup by following certain guidelines and c.) linear compatible I2L is inherently latchup prone, even though the specific device chosen for this study did not latch under radiation.