• DocumentCode
    896072
  • Title

    Dynamic logic CMOS circuits

  • Author

    Friedman, V. ; Liu, S.

  • Volume
    19
  • Issue
    2
  • fYear
    1984
  • fDate
    4/1/1984 12:00:00 AM
  • Firstpage
    263
  • Lastpage
    266
  • Abstract
    A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.
  • Keywords
    Adders; adders; CMOS logic circuits; Clocks; Delay effects; Delay estimation; Frequency; Gallium arsenide; Josephson junctions; Logic arrays; Logic design; Propagation delay;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1984.1052129
  • Filename
    1052129
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=896072