DocumentCode
896268
Title
A fast 16 bit NMOS parallel multiplier
Author
Lerouge, Claude P. ; Girard, Pierre ; Colardelle, Joël S.
Volume
19
Issue
3
fYear
1984
fDate
6/1/1984 12:00:00 AM
Firstpage
338
Lastpage
342
Abstract
An architecture for a fast parallel array multiplier is described. Using a 3 /spl mu/m E/D NMOS process, a 16/spl times/16 bit trial circuit has been designed. A multiplication time of 120 ns has been achieved with a power dissipation of 200 mW and a silicon area of 5 mm/SUP 2/. This architecture concept greatly reduces the logical depth of the array by rearranging internal delays. It is applicable in principle to any MOS, CMOS, GaAs, or bipolar technology.
Keywords
Cellular arrays; cellular arrays; Adders; Circuit testing; Delay effects; Gallium arsenide; Logic arrays; MOS devices; Power dissipation; Propagation delay; Signal design; Silicon;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052147
Filename
1052147
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