Integration of a double-polysilicon emitter-base self-aligned bipolar transistor into a 0.5-μm BiCMOS technology for fast 4-Mb SRAM´s

Author

Hayden, James D. ; Burnett, J.D. ; Perera, Asanga H. ; Mele, Thomas C. ; Walczyk, Fred W. ; Kaushik, Vidya ; Lage, Craig S. ; See, Yee-Chaung

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

40

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

1121

Lastpage

1128

Abstract

The single-polysilicon non-self-aligned bipolar transistor in a 0.5-μm BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits

Keywords

BiCMOS integrated circuits; SRAM chips; bipolar transistors; emitter-coupled logic; integrated circuit technology; silicon; 0.5 micron; 4 Mbit; BiCMOS technology; ECL gate delay; SRAM circuits; Si; base resistance; base-collector capacitance; bipolar performance; double-polysilicon emitter-base; knee current; peak cutoff frequency; self-aligned bipolar transistor; BiCMOS integrated circuits; Bipolar transistors; Bismuth; CMOS technology; Capacitance; Circuit synthesis; Cutoff frequency; Delay; Knee; Random access memory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.214738

Filename

214738