A metal-oriented layout structure for CMOS logic

A design method is described for the realization of large digital modules of random logic for custom integrated circuits in CMOS technology. The layout structure is based on the gate matrix concept with a metal orientation instead of a polysilicon orientation. The symbolic layout is obtained by using 11 different microcells with simple assembly rules. It is derived from the functional specifications of the circuit (Karnaugh maps) using a very simple and attractive method. A CAD program for translating the symbolic layout into a geometrical one is described. It works by assembling geometrical microcells. The advantages and disadvantages of the metal-oriented structure are analyzed through examples of industrial designs. The technique is not suitable for fast circuits. However, it results in an improvement of productivity by a factor of about four and a packing density for large modules which is at least comparable with that of nonoriented hand layouts.