DocumentCode :
896700
Title :
A 16 ns 2Kx8 bit full CMOS SRAM
Author :
Okazaki, Nobumichi ; Komatsu, Takaaki ; Hoshi, Nayoa ; Tsuboi, Kunihihiko ; Shimada, Takashi
Volume :
19
Issue :
5
fYear :
1984
Firstpage :
552
Lastpage :
556
Abstract :
A high-speed 2K/spl times/8 bit full CMOS SRAM fabricated with a platinum silicide gate electrode and single-level aluminum technology is described. A typical address access time of 16 ns, which is comparable to the 16-kb bipolar SRAMs, was achieved. Typical active and standby power dissipations are 150 mW and 25 nW, respectively. The platinum silicide word line reduces the total address access time by 25%. A compact cell layout design, as well as a 1.5-/spl mu/m device feature size, also gives fast access time. The properly controlled bit line swing voltage provides reliable and fast readout operation. The chip size of the SRAM is 2.7/spl times/3.5 mm.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Aluminum; Capacitance; Circuit simulation; Delay effects; Delay lines; Inverters; Platinum; Random access memory; Sheet materials; Silicides;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1984.1052188
Filename :
1052188
Link To Document :
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