A fast 256K DRAM designed for a wide range of applications

Author

Baier, Erich K. ; Clemen, Rainer ; Haug, Werner ; Fischer, Walter ; Mueller, Rolf ; Loehlein, Wolf Dieter ; Barsuhn, Horst

Volume

19

Issue

5

fYear

1984

Firstpage

602

Lastpage

609

Abstract

A 256K DRAM designed for a variety of organizations and operation modes is described. The chip may be organized as 64K/spl times/4, 128K/spl times/2, or 256K/spl times/1. Four data I/O buffers are selectable by gate signals. Besides the standard RAM mode, it may be operated in the page mode, in the parallel or serial buffer mode, and in a combination of page and serial buffer modes. With these options, the design covers a wide range of applications. RAS/CAS access times are 80.55 ns. In the combined page and serial buffer mode, a data rate of up to 50 MHz is possible. The chip is built in metal-gate n-channel technology with 2-/spl mu/m minimum line width and two metal interconnection planes.

Keywords

Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Circuit synthesis; Circuit testing; Circuit topology; Content addressable storage; Costs; Integrated circuit interconnections; Production; Random access memory; Read-write memory; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1984.1052196

Filename

1052196