Title :
A 288K CMOS pseudostatic RAM
Author :
Kawamoto, Hiroshi ; Shinoda, Takashi ; Yamaguchi, Yasunori ; Shimizu, Shinji ; Ohishi, Kanji ; Tanimura, Nobuyoshi ; Yasui, Tokumasa
Abstract :
A 288-kb pseudostatic RAM with high density and ease of use has been fabricated using polycide-gate n-well CMOS technology. For high speed and low power dissipation, a half-V/SUB cc/ precharging scheme, with CMOS back biased to V/SUB BB/, was used. For easier use, an address transition detector, plus auto-refresh and self-refresh, were adopted. Organized as 32K/spl times/9 bits, the RAM occupies an area of 55 mm/SUP 2/ and has a cell size of 6.8/spl times/13.6 /spl mu/m/SUP 2/, which was achieved using the 2-/spl mu/m design rule. A typical address access time is 125 ns, and the operating current is 60 mA at a 125-ns cycle time. Standby power is 2 mA.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Application software; CMOS technology; Circuits; Clocks; Detectors; Manufacturing; Microcomputers; Power dissipation; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052198