Title :
A 128K wordx8 bit dynamic RAM
Author :
Suzuki, Shun Ichi ; Nakao, Masumi ; Takeshima, Toshio ; Yoshida, Masaaki ; Kikuchi, Masanori ; Nakamura, Kunio ; Mizukami, Takeshi ; Yanagisawa, Masayuki
Abstract :
A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Aluminum; Capacitance; Circuit noise; Coupling circuits; DRAM chips; Power dissipation; Random access memory; Testing; Wires; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052199
