DocumentCode :
896898
Title :
A high performance floating point coprocessor
Author :
Wolrich, Gil ; McLellan, Edward ; Harada, Larry ; Montanaro, James ; Yodlowski, Robert A J
Volume :
19
Issue :
5
fYear :
1984
Firstpage :
690
Lastpage :
696
Abstract :
A 34000-transistor single-chip floating-point coprocessor fabricated in 3-/spl mu/m double metal NMOS technology is described. The fraction data path, including a shifter and 60-bit carry propagate ALU, is cycled in 100 ns for all operations requiring less than 19 bits of consecutive carry. A versatile carry length detection scheme, which requires minimal additional logic, is used to extend the microcycle for the small percentage of operations in which a long carry exists. Three-bit-per-cycle multiplication and one-and-one-half-bit-per-cycle division algorithms were used to achieve excellent overall performance.
Keywords :
Field effect integrated circuits; Microprocessor chips; field effect integrated circuits; microprocessor chips; Coprocessors; Gas insulated transmission lines; Hardware; Logic; MOS devices; Microprocessor chips; Packaging; Read only memory; Registers; Semiconductor device measurement;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1984.1052209
Filename :
1052209
Link To Document :
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