A CMOS adaptive line equalizer

A single-chip adaptive line equalizer for a digital transmission system has been developed using a high-frequency switched-capacitor filter technique. The equalizer, consisting of a /spl radic/f and decision-feedback bridged-tap equalizer, is fabricated in a CMOS technology with an effective channel length of 2 /spl mu/m. This permits the use of a 1.6-MHz sampled high-frequency switched-capacitor filter and makes it possible to achieve a small chip size of 6.0/spl times/4.2 mm. This LSI chip can automatically equalize line-loss of up to 42 dB and chemical bridged-tap echoes up to two time slots away from signal pulses at 200 kb/s burst frequency.