DocumentCode
897441
Title
Advanced 5K-gate bipolar gate array with a 267 ps basic gate delay
Author
Suzuki, Masao ; Okamoto, Hidetaka ; Horiguchi, Shoji
Volume
19
Issue
6
fYear
1984
Firstpage
1038
Lastpage
1041
Abstract
To improve performance compared with a previously developed 5K-gate gate array, advanced process technology is used. A 47% smaller emitter window opening technique is used which results in an approximately 0.7-/spl mu/m-wide emitter. Furthermore, the speed-up capacitance of the basic nonthreshold logic cell is increased by 33% over that of the earlier gate array. Consequently, a 17% shorter gate delay of 267 ps, a 22-ps fan-out delay, and a 72-ps/mm load wire delay are achieved with under 1 mW power.
Keywords
Bipolar integrated circuits; Cellular arrays; Integrated logic circuits; bipolar integrated circuits; cellular arrays; integrated logic circuits; Boron; Capacitance; Digital communication; Etching; Logic arrays; Metallization; Paper technology; Power dissipation; Propagation delay; Wire;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052263
Filename
1052263
Link To Document