Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi2 Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET´s. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI´s. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-μm-deep with 2-μm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2μm of polysilicon film. The sheet resistances of N⁺ and P⁺ diffusion and N⁺ -doped polysilicon layers were reduced to 3 to 4 Ω□ by using the self-aligned TiSi₂ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET´s was improved approximately 33 to 37 percent compared with conventional MOSFET´s without the self-aligned TiSi₂ layer. The 0.5-μm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi₂ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static ÷ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.