Defect and fault tolerant interconnection strategies for WASP devices

While WSI-based devices continue to be of particular interest for applications with severe performance, size, weight, power, cost, and reliability requirements, various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization. This paper presents an investigation into defect and fault tolerant interconnect strategies for a representative WSI device, WASP (WSI Associative String Processor)